The present invention relates generally to integrated circuit memory devices, and specifically to methods and apparatus for reducing bit line capacitance and soft error rates in such memory devices.
Large dynamic random access memories (DRAMS) generally comprise an array of memory cells on, or in, a silicon substrate. Each cell typically includes a single metal-oxide semiconductor field effect transistor (MOSFET) with its source connected to a storage capacitor, its drain connected to a bit line, and its gate connected to a word line. The cell operates by storing a charge on the capacitor for a logic "1" and not storing any charge for a logic "0". Traditionally, the cell capacitor has been formed by an inversion layer separated from an overlying electrode by a thin oxide layer and from the substrate by a depletion layer. Alternatively, the cell capacitor can be formed in a trench etched into the substrate. This type of capacitor has the capacitor plates formed on the walls of the trench.
Regardless of the capacitor type used, one concern with such memory cells is the susceptibility of such cells to soft errors caused by a stray electrical charges from surrounding circuitry, or radiation such as alpha particles, striking either the capacitor or the bit line thereby resulting in a change in the charge in the cell being affected.
Another concern with DRAMs is the capacitance of the bit lines. As the capacitance increases, the speed of the memory becomes slower. There is a need therefore to provide reduced bit line capacitance while minimizing the susceptibility of the device to soft errors caused by stray electrical charges.